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| CODEC FOR DIGITAL ANSWERING PHONE S5T8554B INTRODUCTION The S5T8554B consists of on-chip PCM encoders, decoders (PCM CODECs) and PCM line filter. This device provides all the functions required to interface a full-duplex voice telephone circuit, digital answering phone. This device is designed to perform the transmit encoding and receive decoding as well as the transmit and receive filtering function in PCM system. Also it is intended to be used at the analog termination of a PCM line / trunk. This device provides the Band pass filtering of the analog signals prior to encoding and after decoding. This combination device performs the encoding and decoding of voice and call progress tones as well as the signaling and supervision information. 16-DIP-300 16-SOP-BD300 FEATURES * * * * * * * Complete CODEC and filtering system Encoding / Decoding : 8 bits -law PCM On-chip auto zero, sample and hold, and precision voltage references Low power dissipation : 60mW ( operating ) 3mW ( standby ) 5V operation TTL or CMOS compatible Automatic power down ORDERING INFORMATION Device S5T8554B03-D0B0 S5T8554B03-S0B0 Package 16-DIP-300 16-SOP-BD300 Operating Temperature 0C to + 70C PIN CONFIGURATION VBB 1 GNDA 2 16 VFXI+ 15 VFXI14 GSX S5T8554B 13 TSX 12 FSX 11 DX 10 BCLK X 9 MCLK X VFRO 3 VCC 4 FSR 5 DR 6 BCLK R/CLKSEL MCLK/PDN 7 8 1 S5T8554B CODEC FOR DIGITAL ANSWERING PHONE BLOCK DIAGRAM R2 14 GSx VFxIR1 Auto-zero logic Switched Capacitor B.P.F 15 Analog In 16 + RC Active Filter Sample & Hold DAC VFxI+ 11 Dx comparator Voltage Reference A/D Control Logic Xit register DE VFRO 3 Power Amplifier RC Active Filter Switched Capacitor L.P.F Sample & Hold DAC 6 DR Receive register CLK Timing and Control 13 /TSx 4 Vcc 1 VBB 2 GNDA 9 MCLKx 8 MCLKR / PDN 10 BCLKx 7 BCLKR / CLKSEL 5 FSR 2 FSx 12 CODEC FOR DIGITAL ANSWERING PHONE S5T8554B PIN DESCRIPTION Pin No 1 2 3 4 5 6 7 Symbol VBB GNDA VFRO VCC FSR DR BCLKR / CLKSEL MCLKR / PDN MCLKXn BCLKX DX FSX TSX GSX VFXI- VFXI+ VBB = -5V 5% Analog ground Analog output of the receiver filter Vcc = + 5V 5% Receive frame sync pulse. 8kHz pulse train. PCM data input Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master clock in normal operation and BCLKx is used for both TX and RX directions. Alternately direct clock input available, vary from 64kHz to 2.048MHz. When MCLKR is connected continuously high, the device goes powered down . Normally connected continuously low, MCLKx is selected for all DAC timing. Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input is available. 1.536MHz/1.544MHz or 2.048MHz clock input is available May be vary from 64kHz 2.048MHz, but BCLKx is externally tied with MCLKx in normal operation. PCM data output. TX frame sync pulse. 8kHz pulse train. Changed from high to low during the encoder timeslot. Open drain output. Analog output of the TX input amplifier. Used to set gain through external resistor between pin 14 to pin 15. Inverting input stage of the TX analog signal. Non-inverting input stage of the TX analog signal.e Description 8 9 10 11 12 13 14 15 16 ABSOLUTE MAXIMUM RATINGS Characteristic Positive Supply Voltage Negative Supply Voltage Voltage at any Analog Input or Output Voltage at any Digital Input or Output Operating Temperature Range Storage Temperature Range Lead Temperature Range ( soldering, 10 sec ) Symbol Vcc VBB V I (A) V I (D) Ta TSTG TLEAD Value +7 -7 Vcc + 0.3 to VBB - 0.3 Vcc + 0.3 to GNDA - 0.3 0 to +70 -65 to +150 300 Unit V V V V C C C 3 S5T8554B CODEC FOR DIGITAL ANSWERING PHONE ELECTRICAL CHARACTERISTICS (Unless otherwise specified : Ta = 0C to 70C , Vcc = 5V 5%, VBB = -5V 5%, GNDA = 0V ) Characteristic Power Dissipation Power down Current Power down Current Active Current Active Current Digital Interface Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage V IL V IH I IL I IH V OL VIH < VIN < Vcc DX , IL = 3.2 mA SIGR , IL = 1.0 mA /TSX , IL = 3.2 mA , open drain DX , IH = -3.2mA SIGR , IH = -1.0mA DX , GNDA < VO < Vcc8 - - GNDA < VIN < VIL , all digital input - 2.2 -15 -15 - - - - - - 0.6 - 15 15 0.4 0.4 0.4 - 15 V V A A V V V V V A I CC ( down ) No Load I BB ( down ) No Load I CC ( A ) I BB ( A ) No Load No Load - - - - 0.5 0.05 6.0 6.0 3.0 1.0 10 10 mA mA mA mA System Test Conditions Min. Typ. Max. Unit Output High Voltage Output Current in High impedance state ( Tri - state ) Output Resistance Load Resistance Load Capacitance Output Capacitance Input Leakage Current Input Resistance Output Resistance Load Resistance Load Capacitance Output Dynamic Range Voltage Gain Unity Gain bandwidth Offset Voltage Common - mode Voltage Common mode rejection ratio Power supply rejection ratio V OH I OH (HZ) 2.4 2.4 -15 - - Analog Interface with Receiver Filter RO RL CL CL I LKG RI RO RL CL V OD(TX) GV BW V IO(TX) V CM(TX) CMRR PSRR DC test DC test pin VFRO VFRO = 2.5V - - -2.5V Analog Interface with Transmit input Amp 4 CODEC FOR DIGITAL ANSWERING PHONE S5T8554B TIMING CHARACTERISTICS (Unless otherwise specified : Ta = 0C to 70C, Vcc = 5V 5%, VBB = -5V 5%, GNDA = 0V ) Characteristic Frequency of Master Clock System fMCK Test Conditions Depends on the device used and the BCLKR /CLKSEL pin. MCLKx and MCLK tPB = 488ns tPB = 488ns Long Frame only Short Frame only Long Frame only Load = 150pF + 2 LSTTL loads Load = 150pF + 2 LSTTL loads Min. - - - - - 0 0 80 0 - 50 20 50 50 50 160 160 - - 50 Typ. 1.536 1.544 2.048 - - - - - - - - - - - - - - - - - Max. - - - 50 50 - - - 180 140 165 165 - - - - - 50 50 - Unit MHz Rise time of Bit Clock Fall Time of Bit Clock Hold Time for Bit Clock low to Frame sync Hold Time for Bit Clock High to Frame sync Set-up Time from Frame sync to Bit Clock low Delay time from BCLKx High to data valid Delay time to /TSx low Delay time from BCLKx low to data output disable Delay Time to valid data from FSx or BCLKx Set-up Time from DR valid to BCLK x/R low Hold time from BCLK x/R low to DR invalid Set-up time from FS x/R to BCLK x/R low Width of master clock High Width of master clock Low Rise Time of Master clock Fall Time of Master clock Set-up time from BCLKx High (FSx in Long Frame Sync mode ) to MCLKx falling edge Period of Bit Clock Width of Bit clock High Width of Bit clock Low Hold time from BCLK x/R low to FS x/R low Hold time from 3rd period of bit clock low to frame sync (FSx or FSR) Minimum width of the frame sync pulse (Low Level) tR(BCK) tF(BCK) tH(LFS) tH(HFS) tSU(FBCL) tD(HDV) tD(/TSXL) tD(LDD) tD(VD) tSU(DRBL) tH(BLDR) tSU(FBLS) tW(MCKH) tW(MCKL) tR(MCK) tF(MCK) tSU(BHMF) nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS CL = 0 pF to 150 pF Whichever comes later. - - Short Frame sync pulse (1 or 2 bit clock periods long ) : note1 MCLKx and MCLKR MCLKx and MCLKR MCLKx and MCLKR MCLKx and MCLKR 1'st bit clock after the leading edge of FSx - VIH = 2.2V VIL = 0.6V Short Frame sync pulse (1 or 2 bit clock periods long ) : note1 Long frame sync pulse (from 3 to 8 bit clock periods long) 64k bits/s operating mode tCK tW(BCKH) tW(BCKL) tH(BLFL) tH (3rd) 485 160 160 100 100 488 - - - 15,725 - - - nS nS nS nS nS tWFL 160 nS NOTE: For Short Frame Sync timing ,FSx and FSR must go high while their respective bit clocks has high level 5 S5T8554B CODEC FOR DIGITAL ANSWERING PHONE TIMING DIAGRAM Figure 1. Short Frame Sync Timing 6 CODEC FOR DIGITAL ANSWERING PHONE S5T8554B TIMING DIAGRAM (Continued) Figure 2. Long Frame Sync Timing TRANSMISSION CHARACTERISTICS (Unless otherwise specified: Ta = 0C to 70C, Vcc = 5V 5%, VBB = -5V 5%, GNDA = 0V, f = 1.02kHz Vin = 0dBm0, transmit input amplifier connected for unity-gain, non-inverting ) Characteristic Amplitude Response Receive Gain, Absolute GV(ARX) Ta = 25C,VCC = 5V, VBB = -5V Input = Digital code sequence for 0dBm0 signal at 1020Hz f = 0Hz to 3000Hz f = 3300Hz f = 3400Hz Ta = 0C to 70C -1.5 - 1.5 dB System Test Conditions Min. Typ. Max. Unit Receive Gain, Relative to Gv(RRX) Absolute Receive Gain Variations with temperature GV(RRX) -0.6 -0.55 -1.5 - - 0.5 0.5 1.5 0.1 dB GV(ARX) /T - dB 7 S5T8554B CODEC FOR DIGITAL ANSWERING PHONE TRANSMISSION CHARACTERISTICS (Continued) (Unless otherwise specified: Ta = 0C to 70C, Vcc = 5V 5%, VBB = -5V 5%, GNDA = 0V, f = 1.02kHz Vin = 0dBm0, transmit input amplifier connected for unity-gain, non-inverting ) Characteristic Receive Gain Variations with level System GV(RXL) Test Conditions Sinusoidal test method; reference input PCM code correspond to an ideally encoded -10dBm0 signal PCM level = -40dBm0 to +3dBm0 PCM level = -50dBm0 to -40dBm0 RL = 600 VO(RX) VAL VOL(MAX) GV(ATX) GV(RTX) Norminal 0dBm0 level is same as 4- dBm ( 600) Max overload level ( 3.17dBm0) Ta = 25C,Vcc = 5V, VBB = -5V Input at GSx = 0dBm0 at 1020Hz f = 16Hz f = 50Hz f = 60Hz f = 200Hz f = 300Hz - 3000Hz f = 3300Hz f = 3400Hz f = 4000Hz f = 4600Hz and above, measure response from 0Hz to 4kHz Ta = 0C to 70C Min. Typ. - -0.4 -0.8 -2.5 - - -1.5 - 1.2276 2.501 - - -2 -0.5 -0.55 -1.5 Max. Unit 0.4 0.8 2.5 - - 1.5 -35 -25 -21 -0.5 0.5 0.5 -0.5 -10 -25 0.1 dB V Vrms VPK dB dB Receive output drive level Absolute level Max overload level Transmit gain, absolute Transmit gain, relative to GV(ATX) Absolute transmit gain variations with temperature Transmit gain variations with level GV(ATX) /T GV(TXL) - - dB Sinusoidal test method ; Reference level = -10dBm0 VFXI + = -40dBm0 to +3dB0 VFXI + = -50dBm0 to -40dB0 f = 1600Hz f f f f f = = = = = 500Hz - 1000Hz 1000Hz - 1600Hz 1600Hz - 2600Hz 2600Hz - 2800Hz 2800Hz - 3000Hz -0.4 -0.8 - 0.4 0.8 dB Envelope Delay Distortion with Frequency Receive Delay, Absolute Receive Delay, Relative to tD (ARX) tD(ARX) tD(RRX) - -40 -30 - - 90 125 175 - - 315 s 200 s s Transmit Delay, Absolute tD(ATX) f = 1600Hz 8 CODEC FOR DIGITAL ANSWERING PHONE S5T8554B TRANSMISSION CHARACTERISTICS (Continued) (Unless otherwise specified: Ta = 0C to 70C, Vcc = 5V 5%, VBB = -5V 5%, GNDA = 0V, f = 1.02kHz Vin = 0dBm0, transmit input amplifier connected for unity-gain, non-inverting ) Characteristic Transmit Delay, Relative to tD(ATX) System tD(RTX) f f f f f f f = = = = = = = Test Conditions 500Hz - 600Hz 600Hz - 800Hz 800Hz - 1000Hz 1000Hz - 1600Hz 1600Hz - 2600Hz 2600Hz - 2800Hz 2800Hz - 3000Hz Min. - Typ. - Max. 220 145 75 40 75 105 155 Unit s Noise Receive Noise, C Message Weighted Transmit Noise, C Message Weighted Noise, Single Frequency Positive Power Supply Rejection,Transmit Negative Power Supply Rejection, Transmit Positive Power Supply Rejection, Receive NRXC NTXC NSF PCM code equals alternating positive and negative zero, S5T8554B03 S5T8554B03 f = 0kHz to 100kHz, loop around measurement, VFXI+ = 0Vrms - - - 25 - - - - 18 15 -53 - dBrn C0 dBrn C0 dBrn C0 dBC PSRR(PTX) VFXI+ = 0 Vrms, Vcc = 5.0 VDC + 100mVms f = 0kHz - 50kHz PSRR(NTX) VFXI+ = 0 Vrms, VBB = -5.0 VDC + 100mVrms f = 0kHz - 50kHz PSRR(PRX) PCM code equals positive zero Vcc = 5.0VDC + 100mVrms f = 0Hz - 4000Hz f = 4kHz - 25kHz PSRR(NRX) PCM code equals positive zero VBB = -5.0VDC + 100mVrms f = 0Hz - 4000Hz f = 4kHz - 25kHz SOS Loop around measurement, 0dBm0, 300Hz- 3400Hz input PCM applied to DR, Measure individual image signals at VFRO 4600Hz - 7600Hz 7600Hz - 100,000Hz 25 - - dBC - 25 25 - 25 25 - - - dBC dB Negative Power Supply Rejection, Receive - dBC dB Spurious Out-Band Signals at the Channel Output dB -28 -35 - 28 30 25 25 - Distortion Signal to Total Distortion Transmit or Receive Half-Channel THDTX THDRXa Sinusoidal test method; level = 3.0dBm0 = 0dBm0 to 30dBm0 = -40dBm0 XMT RCV dBC 9 S5T8554B CODEC FOR DIGITAL ANSWERING PHONE TRANSMISSION CHARACTERISTICS (Continued) (Unless otherwise specified: Ta = 0C to 70C, Vcc = 5V 5%, VBB = -5V 5%, GNDA = 0V, f = 1.02kHz Vin = 0dBm0, transmit input amplifier connected for unity-gain, non-inverting ) Characteristic Single Frequency Distortion, Transmit Single Frequency Distortion, Receive Intermodulation Distortion System THDSF(TX) THDSF(RX) THDIMD Test Conditions - - Loop around measurement, VFXI+ = -4dBm0 to -21dBm0, two frequencies in the range 300Hz - 3400Hz f = 300Hz - 3400Hz DR = Steady PCM code f = 300Hz - 3400Hz, VFXI = 0V Min. - - - Typ. - - - Max. -41 -41 -35 Unit -dB -dB -dB Crosstalk Transmit to Receive Crosstalk, 0dBm0 Transmit level Receive to Transmit Crosstalk, 0dBm0 Receive level CT(TX-RX) - -90 -75 dB CT(RX-TX) - -90 -70 (note 1) dB NOTE: CT(RX-TX) is measured with a -40dBm0 activating signal applied at VFXI+ Encoding Format at Dx output Encoding Format at Dx Output -Law VIN ( at GSX ) = + Full Scale VIN ( at GSx ) = 0V VIN ( at GSx ) = - Full Scale PCM : S5T8554B 10000000 11111111 01111111 00000000 10 CODEC FOR DIGITAL ANSWERING PHONE S5T8554B APPLICATION CIRCUIT +5V 0.1uF 0.1uF -5V 4 R2 Vcc 2 GND 1 VBB Dx 14 GSx R1 11 Dx 15 VFxIFrom Mic R4 R5 DR 6 DR S5T8554B 3 VFRO MCLKx BCLKx CLKSEL 9 Clock To Speaker R3 10 R6 16 VFxI+ 9 -law only PDN FSx 10 Frame sync 8 PDN FSR 9 NOTES: 1. Supposing desired Line Termination Impedance RL = 600 It is 0 dBm - 0.77459 Vrms 2. Tx Gain = 20 log ( R2 / R1) , R1 + R2 < 100k or The Correspondence of 0 dBm0 = 4 dBm Selection of Master Clock Frequency BCLKR / CLKSEL Clocked 0 1( or Open ) Master Clock Frequency 1.536 / 1.544MHz 2.048MHz 1.536 / 1.544MHz 11 S5T8554B CODEC FOR DIGITAL ANSWERING PHONE NOTES 12 |
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